In synchronous dynamic random access memory (SDRAM) applications, as frequencies approach 200 MHz, the inherent analog delay between an external, system or reference clock and the time output data is valid, is becoming a crucial constraint. Such a delay of e.g. 4-10 ns is large enough to make a following clock cycle overlap the data, i.e. the delay becomes large enough for data not to be ready at the output during one cycle, and it essentially becomes "off-sync". This inherent internal delay must therefore be accelerated according to the necessary frequency but in a controlled fashion. The problem translates into a synchronization task between the internal clock, which controls the output path, and the correct edge of the external clock.
Analog delay locked loops have been employed in the past to perform the synchronization, which are comprised of a delay chain having the delay of its elements varied by analog bias voltages supplied by a phase detector. In digital systems such as memories, microprocessors and application specific integrated circuits, these types of delay locked loops introduce analog design complications in a mainly digital design, and therefore are avoided.
Digital delay locked loops use a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Although digital delay locked loops have a much higher jitter than analog delay locked loops, their ease of implementation in a digital system makes them the preferred solution in most digital applications.
Previously, various digital delay locked loop techniques have been used to address clock synchronization problems, for example as described in U.S. Pat. No. 5,311,483 to Takasugi and U.S. Pat. No. 4,754,164 to Flora et al. Background information concerning digital delay lines is given in U.S. patent application Ser. No. 08/638,809 filed in the name of Maamoun Abouseido and assigned to Mosaid Technologies Incorporated.
U.S. Pat. No. 5,355,037 issued Oct. 11, 1994 to Andresen et al describes a digital delay locked loop, and a representation of key elements thereof is illustrated in FIG. 1. In the disclosed approach, a digital clock waveform is synchronized with a reference clock waveform by propagating the reference clock through a delay path having an adjustable propagation delay. The delay of the delay path is increased from a minimum setting until the edge of the delayed reference clock is eventually time-shifted just past the next corresponding edge of the reference clock. A digital phase detection circuit is employed to control the delay line propagation delay so that the delayed clock remains synchronized with reference clock.
FIG. 1, depicting a common implementation of the prior art, includes: a phase detector 1 comprised of a D-type flip-flop 25, cross-coupled NAND gates 19 and 21 which form an RS flip-flop, AND gates 23 and 28, and a fixed delay circuit 27; a digital delay line 2 which comprises a series of identical delay elements; a right/left shift register 4 having one stage per delay element; internal clock input and output buffers 10 and 12; and, optionally, as further discussed in an application note published by the assignee of U.S. Pat. No. 5,355,037, Texas Instruments, a reference delay circuit 7, and a shift clock generator 8 producing a shift clock signal CLKS with frequency of one half the reference clock frequency CLKR. In the simplest application of prior art, shown in FIG. 1, the Q' output of the phase detector 1 is connected to the "shift right/left" control input of the delay shift register 4. The CLKS signal causes the delay shift register 4 to shift data bits right or left, depending on the state of the phase detector Q', thereby introducing more or fewer delay line elements in the delay line 2 to be connected in series. The delayed output of the delay line 2 is buffered by 12 to form an internal clock CLKI.
The internal clock is optionally connected through a reference delay circuit 7 to the feedback input of the phase detector 1, to introduce a phase shift equivalent to the delays of the semiconductor device input and/or output buffer 10 and 12. This practice is necessary if an internal clock is to be synchronized to a clock external to the semiconductor device.
In operation, with reference to FIG. 2, there exist three relative time positions in which CLKI can be with relation to CLKR. The first case is denoted by CLKI.sub.1, which occurs when the rising edge of the reference clock CLKR 45 trails the rising edge of CLKI.sub.1 46, in which case the rising edge 46 must be delayed to enter into a phase detection window. The phase detection window is denoted by the shaded areas in FIG. 2 and is described in the prior art to be generated by subtracting the propagation delay through AND gate 23 and the setup time of flip/flop 26 from the fixed delay element 27. The second case is denoted by CLKI.sub.2 44, and illustrates the rising edge of internal clock CLKI.sub.2 trailing the rising edge of the reference clock CLKR 45, but rising within the specified phase detection window demarcated by the dashed lines. The third case is denoted by CLKI.sub.3, and occurs when rising edge of the internal clock CLKI.sub.3 43 trails the rising edge of the reference clock 45 and is outside the phase detection window, in which case the rising edge 43 must be delayed past the next rising clock edge 49 and into the next phase detection window. In both cases 1 and 3, delay elements are therefore added to the delay line, causing an increase in the delay. This is accomplished by the logic gates and the D-type flip-flop of the phase detector outputting a 1' to the "shift right/left" control input of the shift register. Therefore, the shift register is clocking in ones and shifting them from left to right. This covers an increase of delay which is continued until a rising edge of the internal clock CLKI occurs within the phase detection window, following the rising edge of the reference clock CLKR, as illustrated in case 2. Once case 2 has been attained, i.e. a 0' output from the phase detector, delay elements are removed from the delay line, effectively decreasing the delay until the rising edge of the internal clock steps just outside of the phase detection window. An increase in delay will then be required and the phase detector will cause the delay line to increase delay once again. This one-step-forward, one-step-backward process is continuously repeated to maintain a locked condition.
The shift right/left control signal applied to the delay line is clocked either by the reference clock or, optionally, for high frequency applications, by a shift clock signal CLKS from the clock divider circuit 8 which runs at half the reference clock frequency. If CLKS is used, the adding or removing delay elements from the digital delay line will occur on every second reference clock signal. The number of delay elements being used in the digital delay line corresponds to the number of sequential 1's stored in the left-most portion of the shift register.
Thus the delay of the delay path is always increased until the rising edge of the internal clock is eventually time-shifted past the next successive corresponding rising edge of the reference clock. It can be seen that the phase detection window used to align the external and internal clock edges is very narrow. When the internal clock is not within the time window, delay is increased continually until the desired edge of the reference clock is time shifted to be within the time window. As described earlier, once the internal clock is within the time window, the system decreases the delay slightly until the internal clock falls just outside the time window, which in turn will cause the system to once again increase delay. The repetitive shifting causes internal clock jitter of one delay step while trying to maintain the lock. It is clearly desirable to minimize this jitter, which implies delay elements with small delays. However, with smaller element delays more elements are required in the delay line to cover the same minimum-to-maximum delay range.
Furthermore, the small phase detection window characteristic of the phase detector, can cause a loss of lock condition if the system clock itself has jitter which will cause the phase detection window to move away from the lock. For example, if the internal clock edge falls within the phase detection window and the system clock experienced jitter, the system will bump the internal clock out of the phase detection window and send it searching for a new lock position by starting to increase delay. In order to solve this problem, the phase detection window for the phase detector must be made no less than two times one delay element delay to ensure lock.
The above prior art circuit thus has deficiencies caused by conflicting requirements. While it has been found to be reliable at start-up of operation, it can easily lose lock when the system clock has jitter, in the manner described above.